The present invention relates to a method of fabricating semiconductor structures and, more particularly, to a method of reducing temperature non-uniformities across semiconductor structures during annealing.
Minimum feature sizes of CMOS semiconductor devices are continuously being reduced. One of the detrimental effects of smaller geometries is short channel and punch-through effects. To overcome these effects, ultra-shallow, abrupt and highly activated junctions are used. However, below the 45 nm node, transient enhanced diffusion (TED) and solid solubility limitations may necessitate stringent junction requirements on annealing processes. That is, annealing may cause diffusion of dopants from the dopant profile created during ion implantation. Conventional rapid thermal annealing (RTA) coupled with low energy implantation have not been successful in fulfilling these requirements. Because of this, alternative annealing processes have been actively investigated. These include non-filament based flash annealing, such as Xenon lamp, and laser annealing techniques.
Flash annealing and laser annealing imparts a significantly smaller thermal budget to the wafer as compared to RTA, because of the smaller pulse duration (in the ms range or less) and because only the near surface region of the wafer surface is heated. As a result, the problem of diffusion from the as-implanted profile during annealing is minimized. However, flash and laser annealing can result in temperature non-uniformities across the wafer surface due to pattern density dependency. That is, the degree to which the wafer is heated varies across the wafer because the reflectance (and consequently heat absorption) of the annealing light varies with pattern density. Pattern density effects result because different materials on the wafer surface reflect and absorb light to different degree. This results in a variance in the annealing temperature across the wafer. By changing the distances between the different structures/materials on the wafer, the temperature profile also changes. The temperature uniformity is thus also affected. These temperature non-uniformities can cause different dopant activations during annealing at different locations on the wafer resulting in an undesirable variance in the performance of identical transistors on different parts of the wafer.
As can be seen, there is a need for a method of reducing the temperature non-uniformity of a semiconductor wafer during flash and laser annealing.